Ali Ghasemi khah - Shahid Chamran university of Ahvaz
Yosef Seifi Kavian - Shahid Chamran university of Ahvaz

In communication systems, ensuring correct information reception is very important, Error Correction Coding methods have been developed in order to achieve this goal. Convolutional Code is used in Wireless, Satellite, mobile phones and Deep-Space communications, it is one of the most powerful Error Correction code, and the Viterbi algorithm is robust way to decode it. Power conception and speed are two important feature of Viterbi decoders, in many communications the power consumption is most important. In this paper, by removing extra decoding cycles, the SMU registers are reduced by ۲۰%, the power consumption reduced by ۱۴.۵% and the speed increased ۶ times without error correction performance loss. The proposed design is described by VHDL and it is implemented on Xilinx Spartan۳, Xc۳s۴۰۰ FPGA chip.

Convolutional code, en, Viterbi Decoder, FPGA, Deep-Space Communication