Decimal Convolutional Code and its Decoder for Low-Power applications
- سال انتشار: 1398
- محل انتشار: فصلنامه ادوات مخابراتی، دوره: 8، شماره: 1
- کد COI اختصاصی: JR_TDMA-8-1_002
- زبان مقاله: انگلیسی
- تعداد مشاهده: 259
نویسندگان
Shahid Chamran university of Ahvaz
چکیده
P. Elias proposed convolutional coding at ۱۹۵۵. Convolutional encoders have very simple structure but their decoders are very complex and power consumer. Power consumption and error correction of Convolutional Codes, will be enhanced by increase in their constrain length, therefore there is always a trade-off between Power consumption and error correction. In Convolutional Codes, the code specifications remain constant in each frame. If the specifications are changed during each frame in a code, a new code with new performance and specifications is created. This paper, aims to evaluate this issue for the first time and compare its performance with Convolutional Codes. This new code is named “Decimal Convolutional”. If in a decimal convolutional code, constrain length is changed during each frame, the generated code will be a convolutional code with “decimal constrain length”. In this paper, a convolutional code with decimal constrain length is introduced, encoder and Viterbi decoder structure is explained for it and its specification is compared with convolutional code. Using this code, an optimized constrain length can be obtained and relative power consumption of decoder can be also reduced. The proposed design blocks are described by VHDL and they are implemented on Xilinx Spartan۳, Xc۳s۴۰۰ FPGA chip.کلیدواژه ها
Low power, FPGA, Viterbi Decoder, Decimal Convolutional Codeاطلاعات بیشتر در مورد COI
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