Masoud kazemy - Device and Simulation Laboratory, Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran,
Morteza Fathipour - Device and Simulation Laboratory, Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran,

we propose a new ESDG thin film SOI LDMOS with an extended-p+ region beneath the source. The first gate is formed over the channel and the second gate is formed over the drift region of the LDMOS. The stepped dual gate structure enhances RESURF in the drift region, and increases breakdown voltage. Based on two-dimensional simulation results, we show that as compared with the conventional LDMOS, the ESDG LDMOS exhibits approximately 138% improvement in breakdown voltage, 68% improvement in on-resistance for gate-source voltage VGS=6V, 26% improvement in peak transconductance and 191% improvement in gate voltage range without any reduction in cut-off frequency.