Mousa Yousefi - Department of Electrical Engineering, Azarbaijan Shahid Madani University, Tabriz, Iran.
Khalil Monfaredi - Department of Electrical Engineering, Azarbaijan Shahid Madani University, Tabriz, Iran.

In this paper, dynamic comparators structure, by employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters, have been presented. The proposed comparators have low consumption thanks to power reduction methods. They have the ability for adjusting the offset. The comparators consume ۱۴.۳ and ۲۴ μW at ۱۰۰ MHz, which is equal to ۳.۷ and ۱۱.۸ fJ. The comparators are designed and simulated in ۱۸۰ nm CMOS. Layouts occupy ۲۱۰ and ۲۴۰ μm۲, respectively.

Efficiency, low-power, Low-Offset, Dynamic Comparator