High Performance Low Latency ۱۶×۱۶ bit Booth Multiplier using Novel ۴-۲ Compressor Structure
- سال انتشار: 1399
- محل انتشار: مجله مهندسی برق مجلسی، دوره: 14، شماره: 2
- کد COI اختصاصی: JR_MJEE-14-2_001
- زبان مقاله: انگلیسی
- تعداد مشاهده: 247
نویسندگان
Department of Electrical Engineering, Ardabil Branch, Islamic Azad University, Ardabil, Iran.
Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran.
چکیده
In this article, the design procedure of a low latency Booth multiplier has been proposed. With the help of a novel ۴-۲ compressor, a high-performance ۱۶×۱۶ bit Booth multiplier has been implemented, which depicts high operating frequency. To achieve this, the proposed ۴-۲ compressor has been utilized successively in the Partial Product Reduction Tree (PPRT) of the multiplier and by means of radix-۴ Booth scheme, the multiplier has been designed. The Partial Product (PP) generation circuitry is also based on the other work published by the authors which enables the designed structure to work at the frequency of ۳۵۰MHz. The main advantage of the designed compressor is the elimination of the middle stage inverters between cascaded blocks of PPRT which considerably enhances the speed of whole system. Simulation results for TSMC ۰.۱۸µm CMOS technology and ۱.۸V power supply have been demonstrated to confirm the correct operation of proposed ۴-۲ compressor. According to the results, the achieved delay of the critical path for hard test and high capacitive load, equal to ۱۰۰fF, is ۹۳۶ps while a power consumption of ۲۵۵.۱۵µW has been achieved at the operating frequency of ۱۰۰MHZ.کلیدواژه ها
Booth Multiplier, Modified Booth Encoding scheme, ۴-۲ compressor, Radix-۴, Low Latencyاطلاعات بیشتر در مورد COI
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