Mohsen Javadi - School of Electrical and Computer Eng., College of Eng., University of Tehran, Tehran, Iran
Nasser Masoumi
Samad Sheikhaei

This paper introduces a method to determine the sizing of the buffers used in the driver of a differential transmission line on chip. Using this technique, the power and delay performance of the buffer is improved, compared with the conventional CML design method. Simulations show that for a differential transmission line with a 138.8fF capacitive and a 73W resistive load, the power-delay product and the rise-time are improved by 169.3% and 14.3%, respectively. The designs are performed in a typical 90nm CMOS technology with a 1.2V power supply

current mode logic, CML, CML buffer design, power and delay reduction, optimization, sizing