Bit-Parallel ECC Coprocessor resistant to Differential Power Analysis Attacks in GF(۲m)

سال انتشار: 1400
نوع سند: مقاله ژورنالی
زبان: انگلیسی
مشاهده: 142

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شناسه ملی سند علمی:

JR_JCSE-8-1_002

تاریخ نمایه سازی: 1 آبان 1400

چکیده مقاله:

Elliptic curve cryptography (ECC) is one of the most popular public key systems in recent years due to its both high security and low resource consumption. Thus, ECC is more appropriate for Internet applications of Things, which are mainly involved with limited resources. However, non-invasive side channel attacks (SCAs) are considered as a major threat to ECC systems. In this paper, we design a processor for the ECC in the binary field, resistant to differential power attacks (DPA). The main operations in this architecture are randomized Montgomery multiplication and division units, which make it impossible to create DPAs by involving a random number in the calculation process. The goal is to accelerate the operation by opening the loops in the Montgomery randomized multiplication/division units, and accordingly, bit-parallel design instead of bit serial design. The results show that, despite the complexity of the logic in the two/three-bit processing versions, the speed is significantly improved by accepting a slight increasing in the area resource. Further, our design is flexible where in the top-level module, depending on the area-speed trade-off, a variety of multiplier and divisor units can be selected. The FPGA evaluations show that in terms of Time×Slice metric, the ۲-bit divider/۳-bit multiplier version of our architecture leads to ۴۰% improvement over the best previous work. Further, by duplicating the divider and multiplier modules along the bit-parallel architecture this gain can reach to ۵۰%. In terms of operation speed, our design versions are faster than previous work by a factor of ۱.۸۷ and ۳.۲۹. Furthermore, ASIC evaluations in term of Time×Area metric, indicate that deploying ۲-bit multiplier leads to ۱۹% gain relative to previous well-known work. Moreover, duplication of modules along with bit-paralleling amplifies the overall gain up to ۳۶%.   

نویسندگان

Hashem Rezaei

Departement of Electrical and Computer Engineering, Tarbiat Modares University, Tehran, Iran.

Alireza Shafieinejad

Departement of Electrical and Computer Engineering, Tarbiat Modares University, Tehran, Iran.

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