A fast settling multi-standard CMOS fractional-N frequency synthesizer for DECT/GSM/ CDMA &/NADC wireless communication standards
- سال انتشار: 1399
- محل انتشار: دومین همایش بین المللی مهندسی فناوری اطلاعات، کامپیوتر و مخابرات ایران
- کد COI اختصاصی: ICTBC02_023
- زبان مقاله: انگلیسی
- تعداد مشاهده: 615
نویسندگان
University of Zanjan, Zanjan, Iran Department of Computer and Electrical Engineering
University of Zanjan, Zanjan, Iran Department of Computer and Electrical Engineering,
چکیده
A fast settling multi-standard CMOS fractional-N frequency synthesizer for DECT, GSM, CDMA and NADC wireless communication standards is proposed. This frequency synthesizer was simulated with ADS2008 in TSMC RF CMOS 0.18 μm. Frequency range is 824-1900 MHz, a switched capacitor LC-VCO was used in order to produce this frequency range. Frequency synthesizers have three main specifications of phase noise, settling time and power consumption. A new channel select circuit was designed instead of ΣΔ modulator to locate spur tones far from center frequency. A high reference frequency was used in order to reduce the VCO phase noise and locate the spur tones far from center frequency; these tones are produced by charge pump (reference spur) and N/N+1 divider (fractional spur). Two ways were used for phase noise optimization; in the first way phase noise was reduced by a low pass filter and a bypass capacitor (CT) that eliminate thermal noise and 2ω0 harmonics of tail current source; in the second way with biasing of VCO transistors only in saturation region preventing reduction of quality factor(Q) in tank circuit. These two ways in VCO of DECT were used, consequently the phase noise at 1875MHz center frequency was improved from-119.4 dBc/Hz at 3.4 MHz offset frequency to -144.3 dBc/Hz at 3.4 MHz offset frequency. The settling time for all standards was achieved less than almost 1 μs over the entirefrequency range. For DECT synthesizer phase noise of - 116.37 dBc/Hz at 3 MHz offset frequency was obtained, the first spur tone was located in 7.35 MHz offset from centerfrequency, also settling time of 350ns was obtained. The whole frequency synthesizer in loop1 (for DECT) draws 13 mA and in loop2 (for GSM900, CDMA & NADC) draws13.67 mA from a 1.8 V voltage supply.کلیدواژه ها
Phase Lock Loop(PLL); Phase noise; Charge Pump; Voltage Controlled Oscillator (VCO); Channel Select Circuit; Programmable dividerمقالات مرتبط جدید
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