Efficient Reverse Converter for Three Modules Set {2^n-1,2^(n+1)-1,2^n} in Multi-Part RNS

Residue Number System is a numerical system which arithmetic operations are performed parallelly. One of the main factors that affects the system’s performance is the complexity of reverse converter. It should be noted that the complexity of this part should not affect the earned speed of parallelly performed arithmetic unit. Therefore in this paper a high speed converter for moduli set {2n-1, 2n+1 -1, 2n} is proposed which is based on Two-Part RNS and Chinese Reminder Theorem. Using this method has increased the speed of reverse converter. To have an accurate comparison both unit gate model and synthesized silicon tools are used and their parameters are compared in terms of delay and area. Converters are implemented in hardware description language and correctness for various n values are verified by simulation and execution on Cadence. As the results show, the proposed circuit has lower delay by around 21% in comparison to previous presented converter.

کلیدواژه ها:

Chinese Remainder Theorem (CRT) ، Computer Arithmetic ، parallel processing ، Residue Number System (RNS) ، R/B converter ، VLSI Architectures